The present invention relates in general to electrical circuits and more particularly to a system and method for signal boosting.
Analog to Digital (A/D) converters are operable to receive an analog input signal and output a corresponding digital signal. It is desirable for the sample and hold circuitry at the front end of the A/D converter to introduce minimal distortion so that a high resolution signal is output from the A/D converter. Accordingly, the input-sampling switch must be highly linear for a large range of input swings. For high frequency sampling of high frequency signals at the input of the A/D converter, signal-dependent parasitic effects can dominate the analog input signal. To output a high resolution digital signal, the A/D converter must minimize these signal-dependent parasitic effects.
Conventional A/D converter designs minimize the signal-dependent parasitic effects using a minimum of two capacitors in a clock multiplier component of the sample and hold circuitry. The sample and hold circuitry may boost the voltage of the analog input signals to minimize the distortion due to signal-dependent parasitic effects. The multiple capacitors occupy a significant amount of circuit surface area. In conventional designs, it is also possible for the voltage output by the sample and hold circuitry to exceed reliability limits, diminishing the performance and digital signal output resolution of the A/D converter.
From the foregoing, it may be appreciated by those skilled in the art that a need has arisen for a technique to boost input signals for an analog to digital converter. In accordance with the present invention, a system and method for signal boosting are provided that substantially eliminate or greatly reduce disadvantages and problems associated with conventional signal boosting techniques.
According to an embodiment of the present invention, there is provided a system for signal boosting that includes a capacitance boosting component. The capacitance boosting component includes a first transistor operable to receive a supply voltage at a gate and a drain and a second transistor operable to receive a clock signal at a gate. The capacitance boosting component also includes a capacitor, wherein a positive terminal of the capacitor is electrically connected to a drain of the second transistor and a negative terminal of the capacitor is electrically connected to a source of the first transistor. The capacitance boosting component further includes a third transistor operable to receive clock signal at a gate and the supply voltage at a source, wherein a drain of the third transistor is electrically connected to the positive terminal of the capacitor. The capacitance boosting component further includes a fourth transistor operable to receive an inverse of the clock signal at a gate and further operable to receive the supply voltage at a source, wherein a drain of the fourth transistor is electrically connected to the positive terminal of the first capacitor. The system for signal boosting also includes a boost component electrically connected to the capacitance boosting component, wherein an output of the boost component is within a selected boost voltage range.
The present invention provides various technical advantages over conventional signal boosting techniques. For example, one technical advantage is to use one capacitor to perform a voltage boosting function that previously required at least two capacitors. Another technical advantage is to significantly reduce the circuit surface area required to implement the signal boosting system. Other technical advantages may be readily ascertainable by those skilled in the art from the following figures, description, and claims.